PRODUCTS

96 FBGA

Macro 

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​DX-MRAM DDR4/5 CHIP FAMILY
The DDR4/5 DX-MRAM Chip Family is a set of MRAMs (magneto-resistive random-access memories) with DX-bitcell architecture. It is fully compatible with the DDR4/5 DRAM chip and capable of completely replacing it.
​DX-bitcell consists of two elements: (1) a novel DX-transistor as a selector and (2) a storage element of whatever sort already produced by fab foundries for emerging NVMs. The DX-transistor is based on a half of a MOS transistor (a 0.5 transistor). Despite this smaller transistor, DX-transistor can drive a higher current for minimizing the area cost of a bitcell and enhancing the speed of bitcell operation. The DX-transistor can be formed on a standard logic process with the sole difference that an additional mask is required in the FEOL (front end of line) processing. DX-bitcell memories, such as DX-MRAM, can therefore be contrasted with DRAM, which requires use of a non-standard process that is costly and limits scalability. Whereas the storage element and logic gates in DX-bitcell memory can be scaled down to 3nm, DRAM faces scaling limitations somewhere around 10nm. Moreover, DX-bitcell memory can easily integrate with CPUs/GPUs/ALUs/glue-logic unlike embedded DRAM.
DX-MRAM has all the advantages of both MRAM and high memory density: fast speed, high bandwidth, low power consumption, low cost, a standard logic process, and highly efficient in/near memory computing through easy integration with CPUs/GPUs/ALUs/glue-logic. Moreover, DX-MRAM allows for instant booting and, since it is an NVM (non-volatile memory), does not lose data when it loses power. Thus, DX-MRAM is the best working memory solution for AI, smartphones, and automobiles.

eDX-MRAM CORE MACRO FAMILY IP
The eDX-MRAM macro family is a set of DRAM-like embedded MRAMs (magneto-resistive random-access memories) with DX-bitcell architecture. These eDX-MRAM macros can be embedded in SoCs and have all the capabilities of SRAM, eFlash, and eDRAM on a single chip. The eDX-MRAM macro is mostly compatible with the DRAM core.​

DX-bitcell TECHNOLOGY IP

Chip Family Features

• Very large capacity per die :

         1Gb/16Gb (DDR4 in dev.)
         32Gb/64Gb/128Gb/
​         256Gb(DDR5 in plan)

• JEDEC compliant in order to displace DDR4/5 DRAM chip (X4/X8/X16 DDR4/5

          FBGA78/96)

• Instantly bootable applications
• No data loss when power off or out
• No refresh operation, decreased power consumption
• Flash/DRAM all in one
• DX-bitcell technology

Macro Family Features

• Very large capacity per macro: 4Mb – 16Gb  in dev./plan
• Mostly compatible with DRAM core
• On chip high band width AI memory macro for in/near memory computing
• Instantly bootable applications
• No data loss when power off or out
• No refresh operation, decreased power consumption
• SRAM/eFlash/eDRAM all in one
• DX-bitcell technology

DX-bitcell Features

• Applicable for RRAM,PCRAM,MRAM, and other emerging NVMs.
• Bitcell architecture: DX-bitcell

          (0.5T+1R)

• Bitcell size: around 2X~7X smaller than the current 1T1R technology
• Process: standard logic process plus one additional mask in FEOL processing for forming DX-transistor
• Scalability: scalable to 3 nm node